The present invention relates generally to use of sample rate converters, and more particularly to use of sample rate converters in audio digital to analog converters (“audio DACs”) in which the audio DAC is not required to be locked in synchronization with the sampling rate of the audio input data.
An audio DAC ordinarily consists of two parts, including a digital signal processing circuit which interpolates (and sometimes performs other processing on) the incoming audio data. The interpolated data may be processed by a digital delta-sigma modulator, the output of which typically is provided as an input to an analog DAC. In conventional audio DACs, the audio data is interpolated by multi-stage interpolation filters and then is fed into a digital delta-sigma modulator. The digital delta-sigma modulator is used to reduce the audio data word width and push quantization noise out of the audio band to reduce distortion caused by nonlinearity of an analog DAC section of the audio DAC. The reduced width audio data words are converted into analog signals by the analog DAC circuitry.
As it becomes more common to store and process audio signals in digital format, the number of applications of audio DACs is rapidly increasing. Various analog audio sources often are sampled at various different sample frequencies and the sampled signals then are digitized to produce various digital audio signals. In digital format, the audio signals can be edited, reproduced and processed easily without introducing nearly as much distortion and noise as would be introduced if the same editing, reproducing and processing were to be performed on the same audio signals in analog format. Also, audio DACs are widely used in applications in which the digital audio samples are played back through speakers and headphones.
Ordinarily, audio DACs operate at clock signal rates that are locked in synchronization with the digital audio input sampling rates, in order to avoid pitch shift artifacts. The effect of the pitch shift artifacts is that the tone at the analog output is not exactly at the frequency it is supposed to be. For example, if the DAC is operating at 48.5 kHz while playing a 1 kHz tone recorded at 48 kHz, the tone at the DAC output will be 1.01 kHz instead of 1 kHz. There are several typical sampling rates for digital audio data, so clock signals related to those typical sampling rates need to be available for clocking the audio DACs to enable them to “play back” the received digital audio at different audio sampling rates. To achieve high quality audio output, the clock signals being utilized need to have low jitter. The jitter of the DAC clock has an FM modulation effect on the audio signals. For example, if the jitter is sinusoidal and the playback audio signal is a tone, there will be two “side tones” at each side of the main audio tone, and the distance of each side tones to the main audio tone is equal to the jitter frequency. In some applications, it is difficult to provide analog DAC clock signals that meet the foregoing requirements. That is, a low jitter clock signal having a frequency related to the audio sampling rate is not conveniently available in some applications.
Also, normally in the prior art a clock signal having a frequency that is directly related to the sampling rate is needed. Otherwise, a PLL (phase locked loop) must be used to generate a sampling-rate-related clock from a clock that is not directly related to the sampling rate. However, it would be highly desirable for some audio DAC applications that any reference signal, such as the output of a free-running oscillator, could be used for controlling the operating rate of the analog DAC section of the audio DAC.
Sample rate converters are necessary for interfacing between devices receiving and/or producing digital signals having different sample rates, in order to avoid audio sample dropping or sample repeating which result in highly undesirable audible “popping” or “clicking” sounds. Even for two devices that receive and/or produce digital signals having the same nominal sample rates but which are based on asynchronous clocks, it is necessary to use an asynchronous sample rate converter to accomplish interfacing between the two devices in order to avoid audio sample dropping or repeating.
In asynchronous sample rate converters it is not necessary that the sample rate of the output signal be synchronized with the sample rate of the input signal. Asynchronous sample rate converters each receive a stream of input samples, process them, and produce output samples when requested, and can be used to convert between any two sample rates irrespective of whether the ratio of the two sample rates is an integer or is a rational number, and irrespective of whether the two sample rates are synchronized.
Because of this feature, an asynchronous sample rate converter can decouple a first digital audio device producing a digital output having a first sample rate from a second digital audio device which is intended to receive the output of the first digital audio device and sample it at a second sample rate. For example, the sample rate of an audio source device might be 48 kHz, and the desired sample rate for an audio destination device might also be 48 kHz, but the clock signals of the audio source device and the audio destination device might be independent and therefore asynchronous. In this case, even though the nominal sample rates both are 48 kHz, a very small drift or difference between the frequencies of the two above-mentioned 48 kHz clock signals will accumulate and cause the above-mentioned undesirable/annoying sample dropping or sample repeating if a synchronous sample rate converter is used.
The prior art is believed to be partially indicated in the assignee's co-pending patent application “ASYNCHRONOUS SAMPLE RATE CONVERTER AND METHOD” Ser. No. 10/325,202, filed Dec. 20, 2002 by Xianggang Yu, Terry L. Sculley and Jung-Kuei Chang, Published Jun. 24, 2004 as Publication No. US 2004/0120361 A1, incorporated herein by reference.
FIG. 1 of the foregoing reference is reproduced herein as “Prior Art” FIG. 1, which shows an asynchronous sample rate converter 1 wherein a memory 6 receives samples representative of the input signal and stores samples thereof at locations determined by a write address wraddr and presents stored samples from locations determined by a read address rdaddr. The presented samples are passed through an interpolation and resampling circuit 7 to produce a continuous-time signal y6 which is re-sampled to produce a signal y7 that is up-sampled relative to a desired output. That signal then is filtered and down-sampled to produce the output signal y. Sample rate estimating circuitry in block 2 computes a difference signal td representative of a time at which a data sample of the audio input signal is received and a time at which a corresponding audio output sample is required, and address generation circuitry generates the read address in response to the difference signal.
A coefficient calculation circuit in block 2 calculates filter coefficients 3 for the interpolation and resampling circuit in response to the difference signal. Asynchronous sample rate converter 1 includes interpolation filtering circuitry 8A,B for receiving a digital audio input signal x having an input sample rate fsin and producing a filtered, up-sampled first signal y2 having a first sample rate 4fsin, and a FIFO (first in, first out) memory 6 for receiving the first signal y2 and storing samples thereof at locations determined by a write address wraddr and presenting stored samples y3 from locations determined by a read address rdaddr. Prior art asynchronous sample rate converter 1 also includes interpolation and resampling circuitry 7 for up-sampling and filtering the presented stored samples y3 to produce a continuous-time signal y6 and for resampling the continuous-time signal to produce an up-sampled discrete-time signal y7 relative to the output sampling rate.
A decimation filter 18 filters and down-samples the discrete-time signal y7 to produce an audio output signal y having an output sampling rate fsout. Asynchronous sample rate converter 1 also includes sample rate estimating circuitry responsive to a main clock MCLK, an input sample rate clock LRIN, and an output sample rate clock LROUT for a computing a difference signal representative of a time at which a data sample of the audio input signal is received and a time at which a corresponding audio output sample is required. Address generation circuitry responsive to an input sampling clock LRIN and the integer part generates the read address rdaddr.
There is an unmet need for a way to more easily utilize audio DACs without requiring the operating frequency of an analog DAC section of the audio DAC to be synchronized with the sampling rate of the audio data.
There also is an unmet need for a way to more easily utilize audio DACs without requiring that a reference signal indicating the audio input data sampling rate be exactly the same as the actual audio output data sampling rate signal.
There also is an unmet need for a way to more easily utilize audio DACs wherein a reference signal of any frequency can be used if the ratio of the reference signal frequency to the audio input data sampling rate is provided.
There also is an unmet need for an audio DAC which does not require an external high-speed operating clock.